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Depending on the process, in a 0.90um process I don't feel it's difficult to meet.
You change some inputs to drive output to change state, then monitor the rise/fall time of mux output to see whether it's 0.5ns behind the rising edge of input.
Hi all,
sachinmaheshwari it is impossible with the conventionnal front end tools so you have to design the mux at transistor level using a analog platform like virtoso cadence.
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