How to build a simple logic gate by using VCVS in Hspice

[shanmei]

Hi,

Anyone knows how to build a or/and/nor gate with VCVS in Hspice commond line( Hspice code)?

The syntax is :

Multi-Input Gates
Exxx n+ n- <VCVS> gatetype(k) in1+ in1- ... ink+ ink- <DELTA=val> <TC1=val>
+ <TC2=val> <SCALE=val> x1,y1 ... x100,y100 <IC=val>

But can anyone give me an example of two input OR gate? Y=A OR B.

I don't want to use veriloga.

Thanks.

 

[dick_freebird]

A simple vcvs has unpleasant consequences if you are
wanting to implement both high gain and constrained
output swing. You would like to have a limiting vcvs
but these are not always offered by a given simulator.
Poly sources can multiply (AND), any vcvs can be
stacked (add, OR), or polarity-flipped (NOT). To make
an emulation that plays nice with the outer world,
that is more the trick.