How to build a capacitor in LEDIT?

[etherios]

I want to build a capacitor in ledit which will be recognised in the extraction. What should i do?

 

[shiowjyh]

l-edit　manual

Hello,
I am not quit familiar with L-Edit; I only can share what I know in magic or virtuoso.
For MIM/PIP in mixed-mode process, it uses a layer of CTM to form capacitor.
For sandwich capacitor in logic process, it uses a layer of CDUMMY to form capacitor.
For MOS capacitor, there is no extra layer to be added.

BTW, as I know. There is no way to extract netlist (LPE), if LVS doesn't pass.

Regards,

 

[Hughes]

how to do l-edit process definition file

Hello,
BTW, as I know. There is no way to extract netlist (LPE), if LVS doesn't pass.
Regards,

LPE can be done before LVS. In fact, an LVS procedure begins with layout extraction, then comes comparison.

 

[Humungus]

ledit id layout

To define a capacitor yu must first define the recognition layer (see ledit manual to see what i´m talking about). Then define the termuinals layers (top and bottom layers of your capacitor). These operations must be performed using the Setup Layers menu.

Create an extraction file following the instructions in the Ledit manual.

You can´t miss it!!!

If further explanation is needed, next week I´ll be able to paste the extraction file.

Regards

 

[etherios]

+ledit +capacitor +layers

Well i tried to do what you said but i was unseccessful. I added in the .ext technology file
device = CAP(
RLAYER=Capacitor ID;
Plus=Metal1, AREA;
Minus=subs;
MODEL=;
) IGNORE_SHORTS

but in simulation i had a message "merging sides" and nothing happened.
Could you please be more specific?

 

[geconom]

mos capacitor design in ledit

I have an answer for you etherios without any modifications in the extract definition files. I use MOSIS/AMI 0.8 technology and the extract definition file in l-edit 10 is mamin08.ext. Towards the end of this file there is the following rule:

# Bonding Area Capacitance
device = CAP(
RLAYER=Pad Comment, AREA;
Plus=Metal1;
Minus=allsubs;
MODEL=;
)

That means that a Metal1 rectangle above substrate is recognized as a capacitor (as happens in reality) if you JUST PUT a rectangle of layer "Pad Comment" on top of it. The capacitor value will be defined by the area capacitance of the "Pad Comment" layer and the area of the rectangles.
Try it to see that it works (I have just done so). Then, change anything you like in the rule to suit your needs.

PM me if you need further help, I can send you a sample layout.

 

[etherios]

capacitor l-edit

Thanks very much geconom, you saved my ass from great trouble, my supervisor would be very angry if i wouldn't come up with something

 

[guamak_menanak]

capacitor in ledit

Fisrt of all, you must make sure the technology that you are using is capable to define the capacitor. What I meen is eventhough by connecting Poly1 and Poly2,we sholud get teh caps value...but if you don't identify the caps area as a caps by the L-Edit menu, the connection is just a mess and the are no ectracted value by the drawing caps! :roll: