Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How to bias the gate to get 6V at the drain an N-mosfet ?

Status
Not open for further replies.

danesh

Full Member level 3
Joined
Nov 24, 2003
Messages
184
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,296
Activity points
1,343
hi,

Im designing a circuit using mgsf1n02lt1 n- mosfet. The vdd would be 13.8V. Can any one suggest how do i bias the gate inorder to get 6V at the drain(output) instead of 0 volt ? Thanks for your concern
 

Mosfet Biasing

Hi
try running a DC sweep - by sweeping the gate voltage and plot output voltage.
but what does the schematic look like? i suppose you got a resistor also, or?
Regards,
Mircea
 

Re: Mosfet Biasing

hi( SALAM )

in mosfets when you give a voltage aproximately above 4V the fet is on.
if the voltage goes upper the curren of fet goes up too.
if you have resistor in drain you can control the Vgs-> to control the fet current -> to control the voltage of resistor ->to gain your consider output voltage

best regards
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top