It's not a big concern to bias the opamp by the bias cell output. The bias current is a common mode signal that should see good rejection from the opamp. This will most probably reduce the loop gain to negligibly small values ( well below 1 ). You can also simulate the loop for PM and GM as well as perform transient step test to make sure everything is stable
you can bias the OP-AMP by the mirrors in the biasing cell and about the stability you can put a compensation capacitance to ensure the stability and you must make stability analysis.