The FPGA has limited clocking resources. For example, a limit of 32 global clock buffers. It looks like the Zynq allows 12 BUFG and 4 BUFR connections per clock region. This limits the number of clocking resources to 32 + 4*Regions total clocks used.
That said, you might be able to increase this limit by some amount. The FPGA also has BUFIO -- these can clock IO resources like the ISERDES. This clock is intended to be routed to a BUFR for use beyond the IO. If the ring oscialltors are slow in comparison to the system clock, you may be able to infer the number of cycles the ring oscillator has performed using the ISERDES module and a LUT to form a johnson counter. This could increase the total number by 4*Banks.