How to avoid glitches in clock gating cell?

[kiranks9]

How to avoid the glitches in clock gating cell? one input is enable and other one is clock source.

 

[dcreddy1980]

clock gating latch

How did you write u r clock gating cell, Do you some thing like the below code :

module clk_gate (clk,enable,q);
input clk, enable;
output q;

reg qd;

always@(*)
begin
if(~clk)
qd = enable;
end

assign q = clk & qd;

endmodule

If you have different technique, let me know !!!

 

[kiranks9]

icg cell

U mean to say add Latch before the AND gate. it means output of latch is goes to one input of the AND gate and other input is clock. Am i right?

 

[dcreddy1980]

latch based clock gating

Thats true !!

 

[yx.yang]

clock gating glitch

Low pass latch + AND can gate the rising edge triggered FF. This will make the enable pin has 1T delay. When use Low pass latch + AND, if you pass STA, there will be no glitch. OR gate can also gate the rising edge triggered FF, if you pass STA, there will be also no glitch.
ps: when use write your own gate module, you'd bettern instance the cell library cell directly, this will disable synthesis tool do optimization on your gate logic. and there may have clock gating cells in your cell library now, may named as ICG cell.

 

[hiral.kotak]

clock gating

Hi,

You can use latch based clock gating style to avoid glitches. Use latch and AND gate combination.
clk and enable signal as inputs of latch, the output of latch will be one input for AND gate and the other input is clk signal. The output od AND gate is propagated to flop as a clock signal.

It may help you.

Thanks..

HAK..

 

[viju]

clock gate latch

Now a days it is command pratice that you should tell your synthesis tool that this is ICG cell (integrated clk gating cell) and put constrain that use clk gating for bus greater than x bit wide. Synthesis tool will take care rest of the things.

 

[Nir Dahan]

glitch clock gating

don't forget the scan issues.
use an OR gate for the enable and the scan enable BEFORE the latch.

ND
https://asicdigitaldesign.wordpress.com/

 

[viju]

clock gating glitches

Nir,
Are you pointing to ICG cells ?,
then I think ICG cells are available with the scan issue provision. ICG cells are available with scan pin option. So ICG cell as whole will take care for all the issues...

 

[hgz]

icg clock gating

Another way use the following logic, it will glitch free.

always @ (negdege clk or negedge rst) begin
if (~rst) begin
en_reg1<=1;
en_reg2<=1;
end
else begin
en_reg1 <= en;
en_reg2 <= en_reg1;
end
end

clk_gate = clk & en_reg1;

 

[navneetgupta]

clock gating cells

If you are using latch..i think timing is more difficult......

 

[no_mad]

clock gating with latch

Hi all,

If you are using latch..i think timing is more difficult......

Any further comments on this.
I'm agree with navneetgupta.

Since, we don't have ICG cell and need to use low pass latch + AND gate as a replacement. During STA, latch must be properly constrained coz it is an async cell.

Please advice.

 

[jaydip]

clock gating issues

Let me give solution conceptually .. I am not sure how much this would be true ..
may be other forum members can completely disagree with it .. but i hope it will give some idea ..

Look at setup and hold time requirements of latch from your tech library ... Constraint your latch input with respect to clock (enable) signal at falling edge appropriately ...

for example, setup time is 12 ps (wild guess) ..

than constraint input of latch like this:
maximum delay allowed for path from previous flop to latch input (give this as a constraint) = clk-q (launching flop) + path delay + letch setup time (12 ps in our case)

probably set_max_delay can do this.

Only thing is you need to calculate delay (for path between launching flop & latch ) values for your self and constraint in .. But this value will change again when you generate new netlist ...

 

[no_mad]

clock gating icg

Hi jaydip,

Thanks for ur reply.

Here i have a suggestion.
Instead of using a latch, we use a negedge flop.

AND gate + negedge D-ff.

Now, someone might ask what happen when clock is transitioning from HIGH to LOW...meta-stability.

Since, after the transition the clock is low and then AND gate.
So, the AND gate will block the unstable flop value for the entire low period of the clock. Plus, it is much easier to do STA later on.
What do you think?

Please shed some light here.

Thanks in advance.

 

[no_mad]

glitch free clock gating

Hi Designers,

Any comments on this issue.

If there is no ICG cell, which is better an AND gate + negedge D-ff or AND gate + a latch??

Thanks in advance.

 

[navneetgupta]

what is a clock gating cell

Hello All,

Please consider the DFT aspect:
If you use simply -ve edge flip-flop in place of latch, in scan chain flop will sample data on -ve edge.

For DFT persons latch is a better option.

But if you use a bypassale clock inversion circuit and then put a +ve edge flop, then i am not able to decide which is better(latch or flop).

As per my understanding we loose some fult coverage in latch but still (not very sure)

Could any one comment.........