flushrat
Full Member level 3
About verilog-A question
In verilog, we can use apply b to a after a time delay: a <= #10 b
But in verilog-A, how can realize it?
Here is the verilog-A code:
integer a;
integer b;
@(V(clk),1) begin
a = b;
end
Simulation shows there should be some delay when applying a to b.
Now my method is apply b to a electrical first, then apply the electrical to a.
But it is quite complicated.
integer a;
integer b;
electrical c;
parameter td=1n;
c <+ transition ( b, td, tr, tf);
@(V(clk),1) begin
a = V(c);
end
In verilog, we can use apply b to a after a time delay: a <= #10 b
But in verilog-A, how can realize it?
Here is the verilog-A code:
integer a;
integer b;
@(V(clk),1) begin
a = b;
end
Simulation shows there should be some delay when applying a to b.
Now my method is apply b to a electrical first, then apply the electrical to a.
But it is quite complicated.
integer a;
integer b;
electrical c;
parameter td=1n;
c <+ transition ( b, td, tr, tf);
@(V(clk),1) begin
a = V(c);
end