How to analyze this voltage buffer?

[butterfish]

Hi, it's a low current voltage buffer that confuse me.

where n5 gives a constant tail current about 40nA. Vout follow with Vref.
My question is: why add n4 here? what's the advantage of this circuit?

waiting for your help,thanks!

fish

 

[rfsystem]

This buffer is long time known as selfbiasing buffer. It is used for buffering signals and consume significant current only if the reference voltage is different from zero. So if Vref is a bandgap voltage activated by switch the buffer consumes only power if Vref > Vth,n. The current mirror loop gain made of p1,p3,n3,n4 should be 2. That is because the diffpair n,n2 divide the current by two. The startup n5 supply only an initial current. The bias current is proportional to Vout/loading.

 

[butterfish]

rfsystem,
thanks for your help.
can i use this buffer for a regulator? by simulation, it seems it is stable with no compesation capacitor, when load current is 1uA, i cant believe that!

thanks again!
fish

 

[rfsystem]

The advantage of this buffer is that it is a single stage opamp connected as buffer but if the mirror ratio mention above is 2 it has the DC loop gain property of a two stage design. The single stage have parasitic pole made by the output mirror and resistive + capacitive (not shown above) load. That does not need compensation. So area could be very low!

 

[butterfish]

do you means,
if p15=1:1, it's a single stage amp, need no compensation;
if p15=1:2, it's a two stages amp, need compendation??

 

[rfsystem]

The mirror ratio (p3/p1)*(n4/n3) should be 2.

 

[avlsi]

I gave also a question,why ur using two diode connected loads. I am new,can u explain why,instead of single diode connected load. Does this help in any way?

And n4 and n5 why there is a need of two transistors.why can't we use only one.