How to analyse this circuit?

[wjxcom]

Hi, all: what is the role of the P-MOS transistor?

Hi, paulux, I have already upload the entire circuit, which includes ed_vbias, ed_OPA_REF, ed_BiasGen.

 

[paulux]

Please include the detailed schematics the building blocks of ed_opa_ref, ed_biasgen & ed_vbias. Otherwise, it is not possible to understand the function of your circuit.

 

[wjxcom]

Hi, all: Is there have no people helps me? Crying!

 

[paulux]

Where is the detailed schematics of each individual block? If you need help, please include these detailed schematics. Otherwise, I will not be able to help you as soon as possible.

 

[wjxcom]

Please see the file ed_Vref.pdf, this file is the top level of this schemetic. The file ed_vbias.pdf is the schemetic that produce bias voltage in the top level; the file ed_OPA_REF.pdf is a OPA of the top level; the file ed_BiasGen.pdf is the schemetic that produce some voltages for the second stage.

Now, I do not know if paulux has already know this circuit and I urgent to get answer from paulux. Help me, Please!!! regards.!!

 

[paulux]

Thx for your description. But what are the detailed circuits inside each individual block? It's almost not possible to understand the circuit without the circuits inside each individual block.

Added after 1 minutes:

or give me email if possible.

 

[ambreesh]

Hi This is what appears to me:
1. ed_vbias: May consist of a constant gm to generate current for biasing and also generate biases for the opamp architecture ed_OPA_REF
2.ed_OPA_REF: Hopefully a singlended folded cascode as it requires 3 bias voltages. ed_OPA_REF along with M13 and C0 and R0 looks more like a internally compensated linear regulator. Node VB would change dependong on process and temperature and supply variations.
3.ed_biasGen: The node VB may be buffered and output drive a resistor ladder from which again voltages are tapped that could be reference for other circuits and these vary as per process, temperature and supply variation.

Hope it helps