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Please see the file ed_Vref.pdf, this file is the top level of this schemetic. The file ed_vbias.pdf is the schemetic that produce bias voltage in the top level; the file ed_OPA_REF.pdf is a OPA of the top level; the file ed_BiasGen.pdf is the schemetic that produce some voltages for the second stage.
Now, I do not know if paulux has already know this circuit and I urgent to get answer from paulux. Help me, Please!!! regards.!!
Hi This is what appears to me:
1. ed_vbias: May consist of a constant gm to generate current for biasing and also generate biases for the opamp architecture ed_OPA_REF
2.ed_OPA_REF: Hopefully a singlended folded cascode as it requires 3 bias voltages. ed_OPA_REF along with M13 and C0 and R0 looks more like a internally compensated linear regulator. Node VB would change dependong on process and temperature and supply variations.
3.ed_biasGen: The node VB may be buffered and output drive a resistor ladder from which again voltages are tapped that could be reference for other circuits and these vary as per process, temperature and supply variation.