u24c02
Advanced Member level 1
Hi.
As I know basically, in synthesis, we can get the information which is WNS,TNS, from start point to end point critical data path from synthesis schematic.
Also mostly in initial synthesis, we focus/concentrate on the setup violation because the hold violation is changed from CTS flow and P&R flow.
But I'm confused that the effect clock skew on setup/ hold time.
how to affect the clock skew on setup and hold time?
As I know basically, in synthesis, we can get the information which is WNS,TNS, from start point to end point critical data path from synthesis schematic.
Also mostly in initial synthesis, we focus/concentrate on the setup violation because the hold violation is changed from CTS flow and P&R flow.
But I'm confused that the effect clock skew on setup/ hold time.
how to affect the clock skew on setup and hold time?