[SOLVED] how to add macro module to DC synthesizer?

[sicheng163]

hi,

I need to design a digital-analog mixed chip,
so when synthesized by DC, I have to add the analog macro .db file,
but I don't know how to get the .db source file, .lib file,
should I write the .lib file myself or there's another way?

thanks!!!

 

[rca]

yes, you need to write your liberty file for your analog macro, and used the library compiler to generate the .db file.
just take care to add the define the correct capacitance, transition, and any timing arc...

 

[sicheng163]

yes, you need to write your liberty file for your analog macro, and used the library compiler to generate the .db file.
just take care to add the define the correct capacitance, transition, and any timing arc...

thanks,
but, it's really hard for to write .lib file,
is there any help file?

 

[lostinxlation]

thanks,
but, it's really hard for to write .lib file,
is there any help file?

You can copy the header part from other .lib file and write a perl or python script to generate pin part. You may need to throw some timing number if the timing is important for your analog-digital interface. Once you generate .lib file, read it into DC and dump out .db file(this loses the functionality of the pins, but since it's an analog block, I guess pin functions aren't important).

 

[kornukhin]

You can also write black-box for you analog block with only directions of pins. Set dont_touch attribute on it while synthesize.
It's easy to implement if you don't care about "the correct capacitance, transition, and any timing arc..."

 

[newmedia]

I think kornukhin's method will be the easiest way, if you are not caring about the timing.

But my question is why you are trying to synthesize the circuit with the hard macro? Is it absolutely necessary?

 

[lostinxlation]

But my question is why you are trying to synthesize the circuit with the hard macro? Is it absolutely necessary?

That's pretty common. For example, you have USB tranceivers in the deisgn you synthesize, or memories or other large macros when you go with hier design. .lib is required because unresolved references are always a trouble. Sometimes, DC looks at the pin directions of macros before doing something and if it can't figure out the pin directions, it could mess up the work. One of the experiences I had was that because of the unknown pin directions of black boxes, scan insertion got messed up.

 

[sicheng163]

That's pretty common. For example, you have USB tranceivers in the deisgn you synthesize, or memories or other large macros when you go with hier design. .lib is required because unresolved references are always a trouble. Sometimes, DC looks at the pin directions of macros before doing something and if it can't figure out the pin directions, it could mess up the work. One of the experiences I had was that because of the unknown pin directions of black boxes, scan insertion got messed up.

Thanks for sharing, I know what to do now, just keep patience to complete my .lib files.

 

[rca]

you should make a script to automaticly generate the script based on your RTL code top.
We defined some key words to add in your rtl code top module, like LIB_AREA, LIB_CAP... to automaticly generate a liberty with user define cap/trans...
But if you have some timing arc to be added, you need to have a better view.
What we do, we used a spice model to generate automaticly the timing arc with some script to start/extract the timing in spice simulation.
good luck