how to add io pads during synthesis?

[vimedu]

Hi guys

I have a sample verilog code and want to synthesize using Design Compilor. And also I want to add IO pads during synthesis.

Is it possible to do this? If possible , what is the procedure?

My inputs are clk, reset, SI and output is outready and PO[7:0]


Thanks in advance

 

[rca]

it is possible, but it's better to test your code with pad to avoid any error when you add the padd connection to your code, and also to properly manage the pad during scan...

 

[vimedu]

Thanks. how do i instantiale IO pads with dc_shell ? What is the method

 

[dianin]

Hi guys

I have a sample verilog code and want to synthesize using Design Compilor. And also I want to add IO pads during synthesis.

Is it possible to do this? If possible , what is the procedure?

My inputs are clk, reset, SI and output is outready and PO[7:0]

Thanks in advance

You have to add IO Pads in your RTL in the same way you add macros (like memories or analog blocks). What you can do create one verilog file consists all IO Pad ports & instance and instaintiate that in your top-level RTL with proper connections.

 

[vimedu]

Thanks for the reply. Now I have modified structural verilog file with proper instances of IO pad and am able to put IO pads in SOCE.