How to add bits of a std logic vector and result should be std logic vector

[amit.kn]

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Code VHDL - [expand]
1
[syntax=verilog]

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[/syntax]


Dear All,

I have a VHDL code in which i am using a std_logic_vector i.e
code:= std_logic_vector(255 downto 0);

I want to add all the bits and store into a vector of 8 downto 0.

Example:

if code = "010101......................0101", suppose we have 90 1's in code then ans should be 90 and should be stored in one more logic vector which is 8 downto 0.




Best Regards
Amit kumar

 

[aruipksni]

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Code VHDL - [expand]
1
[syntax=verilog]

---

[/syntax]


Dear All,

I have a VHDL code in which i am using a std_logic_vector i.e
code:= std_logic_vector(255 downto 0);

I want to add all the bits and store into a vector of 8 downto 0.

Example:

if code = "010101......................0101", suppose we have 90 1's in code then ans should be 90 and should be stored in one more logic vector which is 8 downto 0.




Best Regards
Amit kumar

1. you can sum all bits with adder/s, so "010101" will convert to 1+0+1+0+1 =3. (b"11")...

 

[vipinlal]

run a for loop to add all the bits.

But if you want a synthesisable design, a for loop will not work. In that case you have to do one addition per clock cycle. and you get the result after 256 clock cycles.

 

[TrickyDicky]

run a for loop to add all the bits.

But if you want a synthesisable design, a for loop will not work. In that case you have to do one addition per clock cycle. and you get the result after 256 clock cycles.

You could do it in a single clock cycle just fine using a varaible. Dont expect good FMax results though.

 

[aiza11]

They state that it is a Misspelled variable, signal or procedure name?. Do I have to declare any signal?