ahmad_abdulghany
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ahmad_abdulghany said:Hi,
I want to know steps to add an analog block described in Verilog-A to 'A'DS..
I am assumed to have the verilog-A model written in a text file, and have verilog-A design kit installed,
I will give 100 points as a reward for that,
Thanks alot in advance,
Ahmad,
I want to know steps
Grig said:Hi
You should write ael component definition...
And verilogA based component is working
I have upload example for You
AEL manual (in @DS help) helps to understand "creat_item"
Regards
1.Write verilogA module. I have implement "funy_module" in "vco_fun.va file"
2.Open "vco_fun.ael" file using text editor (wordpad is good choice)
3.Use "creat_item......" block from for ex. vco_fun for template:[\quote]
I'm sorry but what's "creat_item....." block? where to get it?
I think these steps will be easy if i could find the ael file..a)copy this block and paste (the location for paste is Your choice)
b) change //name field----- in my case to "FUNY_MODULE"
c) change //prefix field----- my choice was "funy"
d) change //netlist data field-----in my case "funy_module"
e) change //symbol name
(note: your should creat symbol if it's needed but I have used SYM_INDQ from @DS library (I think it's not needed to explane how to creat symbol))
I am sorry again, but i don't know really how to creat a symbol, explain how to creat it.. this is a point, another point, I don't know how could you find and use symbol of certain componant? where could you get it from?
f) make creat_parm.... string for module parameters (using copy-paste technology) name parameters and change defaults (if you want)
Where to make "creat_param..." from?
I'm really unable to thank you,
Ahmad,
Grig said:Dear Ahmad
I will send WORD DOCUMENT....
But give me some time to prepare it...
Now 25.04.06, I think 26.04 You will have post
Thanks for interesting topic.
Grig said:Dear Ahmand
I will send WORD DOCUMENT....
But give me some time to prepare it...
Now 25.04.06, I think 26.04 You will have post
Thanks for interesting topic.
Grig said:Dear Ahmand
I will send WORD DOCUMENT....
But give me some time to prepare it...
Now 25.04.06, I think 26.04 You will have post
Thanks for interesting topic.
ahmad_abdulghany said:Hi,
I want to know steps to add an analog block described in Verilog-A to 'A'DS..
I am assumed to have the verilog-A model written in a text file, and have verilog-A design kit installed,
I will give 100 points as a reward for that,
Thanks alot in advance,
Ahmad,
I see that years after this post originally was made, the subject is still revisited. I ran into similar problem, but i don't expect that folks that discussed these issues in 2006 would still have that file or plan to send it. So, I set down and figured out how to work with verilog-a in ADS but the process is not straight forward for novice users, so I have prepared my own set of instructions (step-by-step) with screenshots. There are still a few things to figure out that i mention in the document, but i got to a point where i successfully simulated the model that i have created. On an example of a simple DCO (digitally controlled oscillator) i show how to set up the environment and which files to edit (and how to edit).
If there are experts here who know better how to avoid some of the steps that i have shown, please do so, as it would be helpful for me as well.
I am attaching my document.
I see that years after this post originally was made, the subject is still revisited. I ran into similar problem, but i don't expect that folks that discussed these issues in 2006 would still have that file or plan to send it. So, I set down and figured out how to work with verilog-a in ADS but the process is not straight forward for novice users, so I have prepared my own set of instructions (step-by-step) with screenshots. There are still a few things to figure out that i mention in the document, but i got to a point where i successfully simulated the model that i have created. On an example of a simple DCO (digitally controlled oscillator) i show how to set up the environment and which files to edit (and how to edit).
If there are experts here who know better how to avoid some of the steps that i have shown, please do so, as it would be helpful for me as well.
I am attaching my document.
Hi there,
I found your document on VerilogA + ADS quite helpful for beginner like me.
I followed the same steps explained by you, but got stuck in middle. After modifying the ael file in step 11, when I create the new design DCO_test.dsn and add the DCO model, it has instance name x1 (and parameters b0,b1,b2,b3 were not there). I can see in your schematic it is not an issue.... When I add the sources and terminations, and simulate, ADS says incorrect number of terminals... My questions in brief are
a) do we have to include parameter called 'signout' in the modified ael file?
b) Why in my case I can't see the four parameters b0----b3 in the input section?
c) how I can solve the simulation error?
I will greatly appreciate if you can give a reply... Awaiting for your response
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