rkmanju
Newbie level 4
Hi this is Mangulal Nenavath, i have designed a 32 bit counter in VHDL.In my application the counter should work atleast at 250Mhz,but the counter which i have designed is working maximum at 147Mhz.So how to debbug this issue,can any one help me out.
I have contacted Actel technical support they told that with this coding style it is not possible to achieve that(250Mhz) frequency,try for some other coding style. Here the VHDL code for counter.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity cntr_33 is
Port ( clk,trig,reset : in STD_LOGIC;
reg_out : out STD_LOGIC_VECTOR (31 downto 0));
end cntr_33;
architecture Behavioral of cntr_33 is
constant start_value : STD_LOGIC_VECTOR (31 downto 0):=x"00989680";
constant stop_value : STD_LOGIC_VECTOR (31 downto 0):=x"3fffce8f";
constant step_size : STD_LOGIC_VECTOR (31 downto 0):=x"00ff3170";
signal reg_variable : STD_LOGIC_VECTOR (31 downto 0):=x"00000000";
begin
process(reset,trig,clk,reg_variable)
begin
if reset='1' then
reg_variable<=(others=>'0');
elsif trig='1' then
reg_variable<=start_value;
elsif( clk'event and clk='1') and reg_variable<stop_value then
reg_variable<= reg_variable+step_size;
end if;
end process;
reg_out<=reg_variable;
end behavioral;
I have contacted Actel technical support they told that with this coding style it is not possible to achieve that(250Mhz) frequency,try for some other coding style. Here the VHDL code for counter.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity cntr_33 is
Port ( clk,trig,reset : in STD_LOGIC;
reg_out : out STD_LOGIC_VECTOR (31 downto 0));
end cntr_33;
architecture Behavioral of cntr_33 is
constant start_value : STD_LOGIC_VECTOR (31 downto 0):=x"00989680";
constant stop_value : STD_LOGIC_VECTOR (31 downto 0):=x"3fffce8f";
constant step_size : STD_LOGIC_VECTOR (31 downto 0):=x"00ff3170";
signal reg_variable : STD_LOGIC_VECTOR (31 downto 0):=x"00000000";
begin
process(reset,trig,clk,reg_variable)
begin
if reset='1' then
reg_variable<=(others=>'0');
elsif trig='1' then
reg_variable<=start_value;
elsif( clk'event and clk='1') and reg_variable<stop_value then
reg_variable<= reg_variable+step_size;
end if;
end process;
reg_out<=reg_variable;
end behavioral;