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how to achieve our required frequency with the code

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rkmanju

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Hi this is Mangulal Nenavath, i have designed a 32 bit counter in VHDL.In my application the counter should work atleast at 250Mhz,but the counter which i have designed is working maximum at 147Mhz.So how to debbug this issue,can any one help me out.
I have contacted Actel technical support they told that with this coding style it is not possible to achieve that(250Mhz) frequency,try for some other coding style. Here the VHDL code for counter.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity cntr_33 is
Port ( clk,trig,reset : in STD_LOGIC;
reg_out : out STD_LOGIC_VECTOR (31 downto 0));
end cntr_33;
architecture Behavioral of cntr_33 is
constant start_value : STD_LOGIC_VECTOR (31 downto 0):=x"00989680";
constant stop_value : STD_LOGIC_VECTOR (31 downto 0):=x"3fffce8f";
constant step_size : STD_LOGIC_VECTOR (31 downto 0):=x"00ff3170";
signal reg_variable : STD_LOGIC_VECTOR (31 downto 0):=x"00000000";
begin
process(reset,trig,clk,reg_variable)

begin

if reset='1' then

reg_variable<=(others=>'0');

elsif trig='1' then

reg_variable<=start_value;

elsif( clk'event and clk='1') and reg_variable<stop_value then

reg_variable<= reg_variable+step_size;

end if;
end process;

reg_out<=reg_variable;

end behavioral;
 

FvM

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they told that with this coding style it is not possible to achieve that(250Mhz) frequency,try for some other coding style.
That sounds reasonable for a brief answer. Primarly, it's not a problem of coding style rather than FPGA hardware synthesis. You have to understand the available performance of your FPGA family and find a design structure, that can achieve your specification. With simple designs, you don't think about. You write a HDL code and the design compiler does it's work. If you're getting to the speed limits, this doesn't work any more.

The design is basically an accumulator and adder with a fixed increment. The first point would be to find out the achievable speed of the basic 32 Bit adder and accumulator or "counter" for your FPGA family. This can be still done with a behavioral description. It may be the case, that the basic counter is already too fast, then it can be possibly pipelined. Pipelining however changes the behaviour of your component, so you have to modify the instantiating code as well.

If the basic counter works at 250 MHz, then the additional logic involved with start_value and stop_value is probably making it fail. The asynchronous set by the trigger input is at least bad considered, it must be even expected to prevent a reliable operation of the design. Either trig is unrelated to clk, then setup and hold conditions aren't met and start_value won't be set correctly. Or it's related, then it should be replaced by a synchronous preset.

The compare and optional count stop involved with stop_value can be pipelined too, but it's also affecting the "external appearance" of the design.

If you know, how the hardware structure should look like, you can either implement it in HDL or structural code. In a structural style design, it's probably more straightforward, to use blocks from the vendor library e.g. for counter with preset instead of writing behavioral code.
 
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