Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
a) Digital clock manager's an inbuilt resource in most of fpga can be configured to get 180 degree phase shift.
b) Bufgds that is differential signaling buffers which are also inbuilt resource of most of FPGA can be used
Why don't you use a shift register in parallel in parallel out operation? It will give you a output wave with a delay of one clock pulse which is same as 180 degrees phase shift
Why don't you use a shift register in parallel in parallel out operation? It will give you a output wave with a delay of one clock pulse which is same as 180 degrees phase shift
U mean input in registers will be same as clk, right? won't it give timing violations(clk rising/falling edge will coincide with those of input).
This apart if you ignore timing violations(which you shouldn't), don't you think it'll get 360 phase shift??
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
