How to access the internal signals of DUT in VHDL testbench?

[ehsan_iut]

Hi
I've written a testbench for my design in vhdl but I don't know how to access the internal signals of my DUT. Is it possible or we can only have access to the ports? If yes, please help me with the syntax.

p.s. : I want to write them into the file.

 

[lordsathish]

init_signal_spy syntax

which simulator are you using...?
In modelsim you can add signals in design to the waveform...

 

[avimit]

Re: Testbench in VHDL

You can use
'init_signal_spy' if you are using modelsim.
this will allow you to access internal signals from your testbench, and then you may write them into a file.
for full syntax see modelsim guide or search in goolge for 'init_signal_spy'
Kr,
Avi
http://www.vlsiip.com

 

[ehsan_iut]

Testbench in VHDL

I'm using ISE simulator. Is there something like that?