How to access hierarchical name in VHDL

[Leon_Lee]

vhdl hierarchical reference

Hi, guys

I'm a fresh men in VHDL verification.
Can anybody tell me how to access internal hierarchical name in Cadence NClaunch?

I've tried 'Signal Spy' in ModelSim and it works well. Just didn't know how to access internal signals in Cadence and what's the syntax.

BTW, in ModelSim manual it says, "In order to reference internal hierarchical signals, you have to resort to defining signals in a global package and then utilize those signal in the hierarchical blocks in question" ?

Could someone give an example? Thanks

 

[rakko]

in verilog dots (.) are used to access hierarchical pin or signals. For example; if you have a top level design named top with a child block named child and child had a wire named wire, you get to wire from above top like this;

top.child.wire

a similar approach should work for vhdl.

 

[Leon_Lee]

in verilog dots (.) are used to access hierarchical pin or signals. For example; if you have a top level design named top with a child block named child and child had a wire named wire, you get to wire from above top like this;

top.child.wire

a similar approach should work for vhdl.

Thanks, but VHDL doesn't support such hierarchical notation access.
It must need some special packages, i think...

 

[aji_vlsi]

Thanks, but VHDL doesn't support such hierarchical notation access.
It must need some special packages, i think...

Yes, that's correct. Here is a open source package I developed for the same.

http://www.noveldv.com/vcode/probe_pkg.tgz

There is a README file and an example in that tar ball. I have been using it for several years without any issues. I'm yet to update this for VCSMX, in case you use that simulator.

HTH
Ajeetha, CVC
www.noveldv.com

 

[Leon_Lee]

Thanks, but VHDL doesn't support such hierarchical notation access.
It must need some special packages, i think...

Yes, that's correct. Here is a open source package I developed for the same.

h**p://www.noveldv.com/vcode/probe_pkg.tgz

There is a README file and an example in that tar ball. I have been using it for several years without any issues. I'm yet to update this for VCSMX, in case you use that simulator.

HTH
Ajeetha, CVC
www.noveldv.com

Hi, Ajeetha

It works. Thank you.
But, how can i avoid printing NOTE on log file such as:
ASSERT/NOTE (time ***)
The value of obeject :*:*:* has been mirrored to object :*

I've tried to set the parameter 'verbose' to 'false', but it still appears.
The log file looks in mess.

 

[aji_vlsi]

I've tried to set the parameter 'verbose' to 'false', but it still appears.
The log file looks in mess.

Which tool do you use? Can you post a full example?

Ajeetha, CVC
www.noveldv.com

 

[Leon_Lee]

I've tried to set the parameter 'verbose' to 'false', but it still appears.
The log file looks in mess.

Which tool do you use? Can you post a full example?

Ajeetha, CVC
www.noveldv.com

NCsim.
I just didn't want the assert the mirror NOTE in log file.
So i changed the parameter in probe like this
---> verbose => false
My i wrong? I'll try again...

Thanks for your quick response.