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How the jitter performance is improved by designing a VCO with double frequency range

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Oct 10, 2006
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For a better jitter performance it is usually recommended to design a VCO with double the frequency range and divide by 2 and take the output from the divide by 2. How the jitter performance is improved by doing so?
Can anyone explain it??



I have never heard this method can improve jitter performance, it is infeasible

Re: PLL jitter

some where i read this as one of the techniques.
Taking the divider output as PLL output will have a lesser jitter than taking the VCO output as PLL output. I dont know the reason why.


PLL jitter

the dependence of output phase noise is that with increasing divider ratio the output phase noise increases.Its also recommended to keep the VCO gain to only so much as required by the application since more gain adds to more jitter.

PLL jitter

Divide by 2 could get 50% duty cycle clock but could not improve the jitter performance

Re: PLL jitter

It's a little more subtle than that.

Within a given technology family, the phase noise of most frequency sources gets worse as you go up in frequency. There are exceptions (it's not hard to find 100 MHz crystal oscillators that are cleaner than 10 MHz ones, for instance) but not many.

What happens to the phase noise as an oscillator's frequency increases? It's not hard to understand that a given number of picoseconds of jitter caused by noise processes in a given oscillator will raise the phase noise profile of the oscillator by 6 dB if the frequency of the oscillator is doubled without changing anything else.

Likewise, a divider will reduce the effect of a given amount of time jitter on its input signal, improving the phase noise by 6 dB/octave (20*log10(N), to be exact).

So where's the benefit of running your oscillator/synthesizer at a higher-frequency and dividing it down? Doesn't the divider just undo the effect of increasing the VCO frequency? Not necessarily. It's possible to see some improvement because while the VCO's noise may get worse as you go up in frequency, it may not always be as bad as 6 dB/octave.

Common varactor-tuned VCOs are a good case in point. The varactor diode in a VCO has a relatively low Q, which is bad for noise/jitter. You'd like the varactor's contribution to the total LC tank circuit capacitance to be as low as possible. Often, the varactor is in parallel with a fixed capacitor that has much higher Q. So as the tuning voltage -- and hence the VCO frequency -- goes up, the varactor capacitance goes down, becoming a smaller percentage of the total tuning capacitance. This lowers the losses in the tank circuit and keeps the phase noise from suffering as much as you'd expect as the frequency rises.

The phase noise of a wideband VCO like a Mini-Circuits ROS-2150VW isn't much worse at 2000 MHz than it is as 1000 MHz, because it's so heavily-dependent on the varactor in the oscillator tank circuit. So if you wanted a 1000-MHz synthesizer, you could see some real benefits from running your PLL at 2000 MHz and dividing its final output by two.

Even that convoluted explanation leaves out a lot. There is almost always a cleaner VCO available for the original frequency range you're after, if you look hard enough. Digital dividers have their own phase-noise floor, too, which is determined by the semiconductor process. The divider's noise floor is usually much better than any VCO you are likely to use, but if you need to go below -150 dBc/Hz you're going to have to worry about things like that.

Finally, spurs are another good reason to run your synthesizer at a higher frequency and divide it down. Discrete FM spurs benefit from the same 6 dB/octave improvement as phase noise does. Early fractional-N synthesizers in high-end HP gear were sometimes divided by as much as 1000:1 to take advantage of this effect.

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