How the gain of vco influence the jitter of pll?

[xihuwang]

Hi:

In my pll design, the vco 's gain is small for the load cap is bigger than
normal (using H-gate mos transistors) .
So, my question is how badly the low gain of vco will increase the
phase offset between output and reference , and the output jitter ?

 

[saro_k_82]

In a type 2 PLL, it does not affect the static phase offset a bit., and it reduces the output jitter. The static phase offset is created only because of path mismatches in PFD and current and switching mismatches in CP. The control voltage will experience small jumps every reference period and a low KVCO is required to reduce the impact of these reference spurs at the output. In general KVCO should be as low as possible after it fulfills the tuning range requirement.