Feb 11, 2008 #1 S sandeep_sggs Full Member level 2 Joined Jan 21, 2008 Messages 140 Helped 7 Reputation 14 Reaction score 3 Trophy points 1,298 Location india Activity points 2,226 how the delay is incorporated in synthesis?
Feb 22, 2008 #2 S srihari_adem Junior Member level 1 Joined May 24, 2007 Messages 16 Helped 3 Reputation 6 Reaction score 3 Trophy points 1,283 Activity points 1,380 verilog Hi, I think synthesis tool will ignore the delays in RTL..Depends upon ur timing constraints the synthesis tool will pick up appropriate gates from library which accounts for delays. Thanks sri
verilog Hi, I think synthesis tool will ignore the delays in RTL..Depends upon ur timing constraints the synthesis tool will pick up appropriate gates from library which accounts for delays. Thanks sri
Feb 22, 2008 #3 S shiv_emf Advanced Member level 2 Joined Aug 31, 2005 Messages 605 Helped 22 Reputation 44 Reaction score 6 Trophy points 1,298 Activity points 4,106 verilog delays r not synthesiable in DC. It will choose cell n optimize according to constraints