rocking1234
Member level 1
Hi,
The input data rate to the board is nearly 3gbps and the gxb convert this high speed serial data to 40 bits parallel data. I have looked at the gxb architeture that I found it has a CRU[clock recovery unit] that extract the high speed serial clock from the input data signal. and then the pll makes it phase shited to sync with the incoming signal. But my question is how does this CRU recover the high speed clock from the incoming data signal
The input data rate to the board is nearly 3gbps and the gxb convert this high speed serial data to 40 bits parallel data. I have looked at the gxb architeture that I found it has a CRU[clock recovery unit] that extract the high speed serial clock from the input data signal. and then the pll makes it phase shited to sync with the incoming signal. But my question is how does this CRU recover the high speed clock from the incoming data signal