How the bit synchronization in wireless commnunication is implemented in digital IC?

[fanshuo]

Hi,
I want t know how the bit synchronization in wireless commnunication is implemented in digital IC.
I check some papers from IEEE,but they are all for high data speed application, say several hundred Megabit/s.
I am more interested in several Kbit/s speed

Can anybody recommend some document or books that I can refered to?

Thanks guys!

 

[PaulHolland]

Re: synchronization

By means of a digital PLL. I have done this in a microcontroller and what you do is take a timer and capture register and everytime you get an edge you use the capture register to re-load the timer...

 

[fanshuo]

Re: synchronization

I want to know more details of that
like how many different kinds of implementation sychronization?or different PLLs?
what is the pro and cons....

 

[PaulHolland]

Re: synchronization

Hi, You make a digital PLL that is sourced with the datastream and the PLL will lock on the datastream and will also regenerate the clock from the datastream. The PLL can be implemented in the analog domain or digital domain. In the digital domain you can implement it in software or hardware (gates, logic etc). So its up to you to make the choice, most IEEE papers will likely take an FPGA or CPLD since they require speed but since you only need a relatively low speed, software implementation is possible. If the use is for wireless communication you need to take into account that the PLL needs time to recover the clock therefor your transmission needs to be proceeded by 10101010 preamble long enough for the PLL to get locked !

 

[fanshuo]

Re: synchronization

Thanks Paulholland,
I know what yo mean.
But I really need more detailed discussion of the implementation of different PLLs.