how supress off chip 0.1uF in on- chip LDO Voltage regulator

[girih192002]

on-chip ldo

I have design LDO voltage regulator for 1.5V regulated supply with output current max 40mA. But i have problem when i connect this LDO with my other chip module. it's giving oscilliatig regulated output with 1.5V voltage level.while i connect 0.1uF capacitor. i.e off chip it is working fine. the thing is that i cannot connect 0.1uF off chip.beacause, i have to module this design with other design module.
hoe will i overcome of this problem..... ? any body knew it then please let me know..

 

[aryajur]

on chip ldo

You need to figure out a way to compensate your regulator in a better way. The way to compensate would mainly depend on the kind of topology you are using. All Analog IC Design books talk a lot about compensation, otherwise you can post your topology here and we can discuss and try out compensation schemes.

 

[girih192002]

on-chip ldo regulator

Thanks for Comment.

here, i have attach my design file of LDO. Really or it may be i am unable to understand concept of ESR and how to compensate the circuit. so, you guys please help me to resolve these issue. i have open loop gain around 55 dB and close loop gain is around 7 dB. Please let me know.band gap reference voltage is 0.9 volt and supply voltage is 2.2volts.

 

[hung_wai_ming@hotmail.com]

dominant pole compensation nmos regulator

You use PMOS output. It always requires a output cap for dominant pole compensation, so your design is already failed in your approach.
You should use miller cap compensation to make the op-amp pole be the dominant so that you need less cap for output, or u use NMOS as output to further get away the output pole at output. Definitely, your design will be likely fail

 

[watersky]

pmos voltage regulator design

I think your equivalent circuit is not correct. The other chip is not 0.1uF when it works, or it need more current.

 

[girih192002]

regulator op compensation

You use PMOS output. It always requires a output cap for dominant pole compensation, so your design is already failed in your approach.
You should use miller cap compensation to make the op-amp pole be the dominant so that you need less cap for output, or u use NMOS as output to further get away the output pole at output. Definitely, your design will be likely fail

Hello,
Can you tell me how should i do things to compensate the circuit. i really unable to understand concept of miller compensation and dominant pole. so, guys can you help me to do this..? i am reading concept of miller compensation..

 

[qutang]

how do you make your profile back to 0.1

your res net so low.

 

[hung_wai_ming@hotmail.com]

To be honest, your design is a conceptual design, with too small feedback resistor values (460/500), a large DC current and no disable path, with large leakage finally. Your PMOS output is too small (w/l=90u/0.13u), how can u deliver 40mA but still can saturate your PMOS? I can't believe it
You opamp used l=0.13u, how come? Did i see it wrong?
You have 100ohm connected in series with cap=10p, how come? It creates a large ripple!
And 10p to compensate the poly? How come, too small!
Basically, I would consider this is a totally wrong design and should be oscillate. Did u simulate the PM?

 

[rajanarender_suram]

girih ..

Try to use Nmos pass element in your design(output stage) instead of Pmos(since pmos requires output cap to be connected for compensation while Nmos doesnot) , and compensate your opamp properly

 

[arghpok]

Re: how supress off chip 0.1uF in on- chip LDO Voltage regul

This is simply non-possible. I totally agree with huang. If you wanna source 40 mA of current, your aspect ratio should be 32000/1 aprox. Obviously you did not have that. Where is your compensation technique ? I see only a typical error amp (not such a typical one actually) using a Miller cap, and then the output stage. Those resistors, depending on the quiescent current you want and the area you can spend on passive onchip elements, might be in the order of 100~500 kOhms.

If you change your pass element for an NMOS or a npn Darlington config, we're no longer talking about and LDO but a Linear Regulator with large dropout and therefore low effiency.

Maybe you should read power management books first and also take a look at the IEEE database.

PAZ PARA COLOMBIA !