How standard cell characterised for Timing and power?

[n.suresh60]

Can anybody give details on standard cell characterisation for timing and power, if have any document share .


thanks in advance..

 

[jbeniston]

You run a library characterisation tool, like Synopsys Liberty NCX or Cadence Encounter Library Characterizer.

 

[n.suresh60]

I'm not running tools.
I'm a pd engineer, i want to know about how characterization is done for the standard cells.
and .lib format

 

[jbeniston]

You run one of those tools, which run spice using the netlist for the standard cells, and then they generate the .lib for you.

 

[n.suresh60]

thanks@jbeniston
and i also need information on how exactly the timing and power characterization is done.?

for example:
how a cell delay is calculated based on the reference pins. and same for power?

 

[jbeniston]

It's pretty much automated by the tools. You just give them the spice netlist and corner info, it then runs spice to work out the delay and power.

 

[n.suresh60]

yes but i want some examples theoritically calculating cell delay with considering corners..

 

[artmalik]

You have to read the manual of liberate or siliconsmart. there are many engineers employed by companies to do this. as such PD engineers don't need to know ....." the data is generated as the information is not that useful to them. it is detailed and compute intensive task.
some guidelines :
delay: 7input slews and loads used for inverter and delays is calculated for each of them and put in the .lib
power : current is integrated over the rise/fall times and put as energy in the .lib
setup/hold : the data input is swept till it violates the setup and hold times of the flops for each slew in the design.
The slews/loads change depend on the voltage temp etc. there are standard "methodologies" that have been established and the commercial tools use them to generate the data for the .lib.