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ncverilog command line option
Dear all,
I am using NC-verilog to simulate our design (about 3M gate).
For almost function-patterns, only a few stimulus are changed.
although when ncvlog phase,I separated library,gate and top
bench(includes stimulus), ncelab still costs a long time.
Can anyone tell me a way to speedup my simulation wth my
case.
Thanks
Dear all,
I am using NC-verilog to simulate our design (about 3M gate).
For almost function-patterns, only a few stimulus are changed.
although when ncvlog phase,I separated library,gate and top
bench(includes stimulus), ncelab still costs a long time.
Can anyone tell me a way to speedup my simulation wth my
case.
Thanks