How sdc affect the sdf

[qqxiu]

Hi all,

After APR, i used Primetime to generate the sdf file for postsim.
It seems that we need to prepare the sdc file to generate the sdf file.
In my design, i have different mode, so i have different sdc file.
I wondering that what kind of the sdc that is needed to generate a reliable sdf ?
Hope someone can point out that something that i misunderstood.

 

[ThisIsNotSam]

You always need at least one SDC to model clocks, input/output relationships, and a lot more. it is not that the SDF relies on the SDC file directly. Everything during the place and route phase relies on the SDC. It is mandatory.

 

[qqxiu]

You always need at least one SDC to model clocks, input/output relationships, and a lot more. it is not that the SDF relies on the SDC file directly. Everything during the place and route phase relies on the SDC. It is mandatory.

Hi ! Thanks to your reply.
I was wondering if it is OK to provide less constraints in generating SDF.
For example, we need to eliminate the set_case_analysis constraint.
I want to know that which constraint should not be reduce in generating SDF.

 

[ThisIsNotSam]

depending on what your set_case_analysis is, you would generate two SDFs, one for mode A and one for mode B.

 

[pmjpvprasad]

depending on what your set_case_analysis is, you would generate two SDFs, one for mode A and one for mode B.

What will be the difference in mode A and mode B SDF, when netlist is same. Will cell delay and interconnect delays varies with modes?

 

[ThisIsNotSam]

this is entirely design dependent. let's say you have a pin named low_power_mode that turns off a lot of things in your design. and let's say you have an SDF for when all features are being exercised at fast speed (all modules are ON) and another SDF when only a subset of the features are being exercised at low speed (some modules are OFF and clock is much slower). Netlist is indeed the same, but the operation of the design is completely different.

 

[pmjpvprasad]

How does clock speed affect cell delays in SDF? On silicon, cell delay will depend only on the PVT corner, right?

How can two different modes(let say case analysis doesnt affect power) with different frequencies have different cell delays?

 

[ThisIsNotSam]

in general, we can say it does not affect.

however, it does in a very narrow sense. note that individual cell delay is a function of process, output load, and input speed/slope. A slower clock might also have slower 0->1 ramps, which affects how the clock tree propagates clk signal and finally affects how the flops latch data.

 

[pmjpvprasad]

Thank you for your response.

Is below scenario possible?

Let say clock frequency is different in two modes, derates in this two modes will be different. Based on differences in derates cell delay may vary in two SDFs.