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how scan chain will effect the design

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naribtech

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Hi All,

I am new trainee in PD . I have a doubt, what is scan chain. what is scan reordering ? is it effect the utilization of the design ? if its effect how it will be?


Thanks,
Narendra
 

phoenixpavan

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Hi Narendra,

Scan Chain is used for Testing the chip. It is a DFT technique. It consists of a chain of f/f connected together to test the circuit.
The order of these scan cells can be reordered for optimization.
1. Placement aware: based on scan cell locations so that scan chains contain components that are near each other. Helps in resolving congestion and net delay issues
2. Clock aware: to minimize clock buffer crossings which can help in hold fixing in scan chain

Yes it will effect the utilization as sequential elements in the design are replaced with scan cells(Muxed D f/f)...and % variation depends on the no of scan chains in the design..

Hope it is useful..
 

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