How scan chain testing is done?

[Madhusudhan.R]

how scan chain testing is done?
How faults are detected using test vector & how patterns are compared so that we can find mismatch in test patterns?

 

[moottii]

By using JTAG we are able to detect any fault in the chip.How? look at the below picture

**broken link removed**

As you see, JTAG injects some vector to see the correctness of the chain. If the chain has any problem, the output vectors aren't the
same as input vectors. So we understand that there is some problem.
You can read a lot more about JTAG in the web.

 

[rca]

Well, JTAG and scan chain could be related but not mandatory.
Scan chain only means all flops are directly connected together t be able to load a certain state, and after that doing a clock capture and shift out the capture value to check the logic work as expected.
The JTAG is a typical ports for test purpose, which could be used to place the chip in scan mode, and used TDI->TDO as scan chain.

 

[maulin sheth]

What do you mean by Scan Chain Testing?
Do you want to know how we can test the scan chain means additional hardware for scan chain is properly working or not?

If you mean this, thn scan chain is tested by pattern itself.Mostly TetraMAX ATPG generates the first pattern for scan chain testing by default.
So through this, we know that scan chain is properly working fine.These pattern is also known as flush pattern.

What is scan chain..than read the rca answer.

 

[rca]

As indicate by maulin sheth, the ATPG tool (tetramax or fastscan), the first pattern shift-in is normaly very basic 0011..., and there is no clock pulse during the capture phase, then the second shift-out will provide the same patterns 0011... . By this the scan connection and ATE connections to the chip is verified.
The basic pattern could be modified in the tool.

 

[ro9ty]

Could you also tell about the clock relations i scan shift, scan capture and at-speed modes?
I mean i have seen that capture clock could be same as functional clock (frequency) but shift is slower... why ?

 

[rahul.achates]

When you say scan chain testing ... it has lot of meaning, so please be specific.
ing
I think u are asking about the stuck at 0 or stuck at 1 scan testing , there are 2 types of testing,

1. transition testing
2. stuck at 0 or stuck at 1 testing


stuck at 1 or 0 , you need to generate a pattern called test vectors , those vectors are generated by tool itself but you can configure which type of pattern you want , then those patterns will drive into test inputs and monitor at test output.

if you want to know more, you can search stuck at 0/1 and search for capture cycle which is a basic concept in scan testing.

hope this will help you understand scan chain testing .. this is vast topic and can't cover in forum, you need to download more material and understand it.

Let me know if you have any specific question -

 

[ro9ty]

Thanks,

Yes i am referring to stuck at 0/1 violations only. I have read about the test vector generation, ATPG etc... However, i just wanted a little bit of clarity on the clocks used for scan. I will explain my dilemma. When we do STA for scan paths, we can do scan capture with functional clock (ex. say 100MHz) but for scan shift we use a slow speed clock (ex, say 10MHz) Why exactly?
A little explanation on scan capture and scan shift would be better in clearing my doubts.
Could you please attach some documents if you have.

Congratulations with your block. Keep up the good work.

 

[rahul.achates]

there are 2 type of scan testing , stuck at 0/1 and transitioning testing.

Stuck at 0/1 is mainly to check the manufactured defect in flop which can be done at slow frequency. so if a design doesn't have transitioning testing then timing can be closed at slow frequency (10 MHz normally), this save a lot of hardware.

but if a design need to do transition testing , which actually done at functional clock frequency and will increase hardware in chip. the basic difference is , stuck at 0/1 perform to find the manufacturing defect but transition testing is done to check transition at each node , patters are different for both.

I am not sure if we operate shift cycle and capture cycle at different clock frequency , may be you can go through below pdf
**broken link removed**


Rahul J