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Negative skew means, clock is reaching capture flop is faster than the launch. So you have small timing window to meet the timing. In other words possibility of setup violation will increase, so ultimately your frequency will reduce….
i think due to the negative skew clk freq increases.
tclk>tc-q+tcomb+tsetup+tskew (for negative skew)
tclk>tc-q+tcomb+tsetup-tskew (for possitive skew)
Negative skew means, clock is reaching capture flop is faster than the launch. So you have small timing window to meet the timing. In other words possibility of setup violation will increase, so ultimately your frequency will reduce….
I have never used any equation for STA. so I cannot put explanations in equation properly. I will try to put some rough equation
Required time = clock cycle + skew – setup time of a flop
Setup violations = required time – arrival time
So if your skew is negative, required time will be less, so probability of violating setup is more. More the violation lower the frequency of a circuit.
What I personally feel, don’t go with equation, equation will always confuse you ( I get confuse with equation :wink: ). Get a feel of STA. it will be better.
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