Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How negative Skew effects frequency

Status
Not open for further replies.

kunal1514

Full Member level 1
Joined
Dec 13, 2006
Messages
98
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
2,027
Hi All,

Can any body tell me How negative skew effects frequency
 

shelkerahul

Member level 4
Joined
Feb 8, 2005
Messages
79
Helped
10
Reputation
20
Reaction score
6
Trophy points
1,288
Location
Bangalore
Activity points
581
Negative skew means, clock is reaching capture flop is faster than the launch. So you have small timing window to meet the timing. In other words possibility of setup violation will increase, so ultimately your frequency will reduce….

Hope explanation is clear enough….
 

nikhilindia85

Member level 4
Joined
Feb 28, 2007
Messages
78
Helped
3
Reputation
6
Reaction score
3
Trophy points
1,288
Activity points
1,712
i think due to the negative skew clk freq increases.
tclk>tc-q+tcomb+tsetup+tskew (for negative skew)
tclk>tc-q+tcomb+tsetup-tskew (for possitive skew)
 

kunal1514

Full Member level 1
Joined
Dec 13, 2006
Messages
98
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
2,027
Shelkerahul

Has written

Negative skew means, clock is reaching capture flop is faster than the launch. So you have small timing window to meet the timing. In other words possibility of setup violation will increase, so ultimately your frequency will reduce….

Hope explanation is clear enough….

Can u explain this thru some equation i will be thankful to u.
 

shelkerahul

Member level 4
Joined
Feb 8, 2005
Messages
79
Helped
10
Reputation
20
Reaction score
6
Trophy points
1,288
Location
Bangalore
Activity points
581
I have never used any equation for STA. so I cannot put explanations in equation properly. I will try to put some rough equation

Required time = clock cycle + skew – setup time of a flop

Setup violations = required time – arrival time

So if your skew is negative, required time will be less, so probability of violating setup is more. More the violation lower the frequency of a circuit.

What I personally feel, don’t go with equation, equation will always confuse you ( I get confuse with equation :wink: ). Get a feel of STA. it will be better.
 
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top