boardlanguage
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systemverilog synplify
I've been using Altera Quartus-II 7.1 web-edition to synthesize some hobby projects. I hope one of these becomes commercially usable, but I have a big obstacle.
Since I wanted to learn some Systemverilog, I wrote all the RTL in Systemverilog 3.1a (though it can be downcoverted to Verilog-2001 pretty easily.) Quartus-II supported just enough systemverilog for it to be worth my time to even write the RTL this way.
Xilinx XST 9.1 doesn't support Systemverilog at all. (I heard Systemverilog synthesis is planned for the 10.x release.)
... so that brings my question to the 'third-party' FPGA synthesis-tools: Synplicity, Mentor, Synopsys. I know Synopsys supports Systemverilog quite well -- I'd consider them the 'gold-standard' (thus far.)...
but what about Synplicity? How does their Systemverilog support compare to the other vendors?
I've been using Altera Quartus-II 7.1 web-edition to synthesize some hobby projects. I hope one of these becomes commercially usable, but I have a big obstacle.
Since I wanted to learn some Systemverilog, I wrote all the RTL in Systemverilog 3.1a (though it can be downcoverted to Verilog-2001 pretty easily.) Quartus-II supported just enough systemverilog for it to be worth my time to even write the RTL this way.
Xilinx XST 9.1 doesn't support Systemverilog at all. (I heard Systemverilog synthesis is planned for the 10.x release.)
... so that brings my question to the 'third-party' FPGA synthesis-tools: Synplicity, Mentor, Synopsys. I know Synopsys supports Systemverilog quite well -- I'd consider them the 'gold-standard' (thus far.)...
but what about Synplicity? How does their Systemverilog support compare to the other vendors?