How many rows of contacts will you layout ESD MOSFET?

[prcken]

Hello, all
How many rows of contacts will you layout ESD MOSFET at the drain side?
i saw the ESD design rule provided by some foundry shows only one row of contact, dont you think that is too weak to sustain large tranisent ESD current?
i've some statics to show that it's better to use more than one row of contacts at the drain side of the ESD device.
what's your experience?
thanks and best wishes
Kehan

 

[dick_freebird]

If current flow is vertical than more contacts helps. But if it is
lateral then any behind the first rank will be debiased at
higher currents, and you want more fingers of one apiece.

You should have or arrive at a current per contact, current pe
micron ESD rules set and drag that comb all the way around
the ESD current loop. But sometimes numbers alone do not tell
the story.

 

[prcken]

If current flow is vertical than more contacts helps. But if it is
lateral then any behind the first rank will be debiased at
higher currents, and you want more fingers of one apiece.

You should have or arrive at a current per contact, current pe
micron ESD rules set and drag that comb all the way around
the ESD current loop. But sometimes numbers alone do not tell
the story.

hi, flow vertical means there is a 90 degree detour when the current flow from metal/drain terminal to source terminal (as the arrow in the attached picutre shows )?

 

[mikersia]

Number of drain contacts also depends drom ESD protection design strategy. For example, if primary protection is based on PMOS/NMOS into breakdown mode, then you need balasting resistors (a few ohms per finger) on drain side. It can be implemented in different manner. One of e.g. is so called "back-end ballasting", proposed by Sofics,- it is a chain of intelayer contacts. So number of contacts can be optimized
for such type of primary protection.

 

[prcken]

Number of drain contacts also depends drom ESD protection design strategy. For example, if primary protection is based on PMOS/NMOS into breakdown mode, then you need balasting resistors (a few ohms per finger) on drain side. It can be implemented in different manner. One of e.g. is so called "back-end ballasting", proposed by Sofics,- it is a chain of intelayer contacts. So number of contacts can be optimized
for such type of primary protection.

hi, thanks for your reply
how about if i use ordinary protection strategy, for example ggnmos with SAB mask layer?

 

[mikersia]

in that case one row typically should be sufficient, but you should check electromigration criteria for spec requirements,- e.g. for automotive temp range (at 175) allowed current density can be drastically lowered.

 

[prcken]

in that case one row typically should be sufficient, but you should check electromigration criteria for spec requirements,- e.g. for automotive temp range (at 175) allowed current density can be drastically lowered.

yes, i saw only one row contact for the drain of ESD device in serveral products. and the ESD rule provided by the foundry also shows one row of contacts in the document.
we are doing low-power consumer electronics, the temperature wont exceed 175C. so can i ignore electromigration effect?
my point is i dont think the foundry provides the optimal or high performance ESD design rule. because i have test TLP data shows with 4 or 5 rows are far more robust than the one row contact device. but there are other parameter variations like W are different so that i cannt account on the test reults for exact comparison, i am not sure whether the contact effect outweighs other parameter effect in terms of ESD performance.

 

[mikersia]

really, foundry guides incorporates minimum necessary requirements. Usual practice for I/O design is to use a lot of contacts, oftenly mach bigger than necessary. But estimation of a proper quantity by simulations isn't realistic task, so overestimation is typical.

 

[erikl]

... you should check electromigration criteria for spec requirements,- e.g. for automotive temp range (at 175) allowed current density can be drastically lowered.

In principle this is correct, however for ESD protection circuitry I think you need not care about - unless you fear of permanently and frequently recurring ESD events ;-) : electromigration ~ current_density * time.
But of course the number of contacts/vias should be sufficient for the max. expected current. And if you can't get enough contacts within one row, I think it's better to spend more fingers than another or even more contact rows - as dick_freebird already suggested above.

 

[dick_freebird]

A row with multiple contacts may survive because more
contacts means more metal. However the effectiveness,
as ESD_voltage*contacts, is liable to be degraded if shrouding
or debiasing becomes real.

By vertical I mean Z axis, into the substrate (as some
devices like substrate diodes would do). But in the plot the
Y axis (finger length) also will induce some longitudinal
debiasing. If you take current out of the same end then you
see a twofold debiasing which can make the far end of the
structure less effective, and hot-spot the near end. It is better
to have entry and exit on opposite sides so that the debiasing
cancels.

Single pulse current density can be on the order of 100X the
DC electromigration limit without failure. In addition to the time,
normal depowered ESD testing is not done at high temp.
However if you are running current densities that are any
kind of "interesting", you're also dropping a lot of voltage
in the interconnect most likely. That has to be an allocation
along with steering diode and clamp drops, the sum being
below transient BVOX. Fat metal good.

Some processes have pretty poor contact step coverage
and metal that crosses a contact can be less than half its
natural cross-section. Running larger than minimum overlap
is good (no reason not to push it out to min spacing usually,
even if contacts only occupy a sliver down the middle).