How many inputs can be driven by a FF in a FPGA?

[samuel_john]

load on signal

hi
if we consider the internal logic inside an FPGA....normally how many inputs can be driven by a FF..and on what factor does it depends.

when does register duplication happens...


thanks

 

[xfpgas]

Re: load on signal

hi
if we consider the internal logic inside an FPGA....normally how many inputs can be driven by a FF..and on what factor does it depends.

when does register duplication happens...


thanks

Routing Resources is the limiting factor. If you have high fanout nets, you will end up with large routing delays. XIlinx tools let you limit the Fanout in their options. I am not sure what else are the limiting factors.

Hope this helps.
Kode