How many gates are there in a macro cell of Xilinx CPLD?

[blue_phoenix]

does anybody know how many gates there are in a macro cell of Xilinx CPLD?

Is Logic element and Gate the same?

thanks in advance for your help.

 

[echo47]

macro cells

A logic element is usually a larger structure than a single gate.

Unless someone is requiring you to count gates, I suggest forgetting about gate count in FPGAs. Years ago, I asked two Xilinx field application engineers about gate count, and they simply laughed. Better to count slices, IOBs, Block RAMs, multipliers, DCMs, and other tangible resources.

When I'm selecting an FPGA for a signal processing project, the first things I count are flops, multipliers, and Block RAMs.

UPDATE

Oops, you did say CPLD. I must have spaced-out and thought "FPGA".
The situation is similar, though. It's better to count tangible resources (I/Os and macrocells) than gates.

 

[vikasbb]

Re: macro cells

Hello
Gate count varies cpld to cpld,which device gate count u want?
for this simple way is go through data sheet of the device.

 

[banjo]

macro cells

Hi,

For the 95 series of CPLDs the number of macro cells is built into the part number. For example, the 9572XL has 72 macro cells. Each macro cell has a single flop and a single wide AND array. The AND array and flop can be used together or each separately. Ignore the data sheet stuff about gate count. It is always misleading.
The biggest limitation for Xilinx CPLD is the one flop per macro cell limit. 72 flops is not alot especially when you try to do things like FIFOs or memory. CPLDs are NOT miniature FPGAs. FPGAs have a large, large number of internal LUTs and flops. CPLD have their logic restricted to macro cells at the IOB.

 

[fguihot]

Re: macro cells

Hi,

For the 95 series of CPLDs the number of macro cells is built into the part number. For example, the 9572XL has 72 macro cells. Each macro cell has a single flop and a single wide AND array. The AND array and flop can be used together or each separately. Ignore the data sheet stuff about gate count. It is always misleading.
The biggest limitation for Xilinx CPLD is the one flop per macro cell limit. 72 flops is not alot especially when you try to do things like FIFOs or memory. CPLDs are NOT miniature FPGAs. FPGAs have a large, large number of internal LUTs and flops. CPLD have their logic restricted to macro cells at the IOB.

Hello !!!
In my opinion (I am used to work with Altera CPLD, but novice with fpga), the main advantage of CPLD upon FPGA is the fixed input to output delay, which is independant of the implemented logic. (for one logic stack, of course...)
The 2 main drawback are in my opinion that the logic ressource are more limited, but you could use the AND array to build your own flops.
The other point is the routing matrix, which is most of the time incomplete. Thus, there are always logic ressources that you couldn't use, and it is hard to use more than 75% of the logic materials...