For the 95 series of CPLDs the number of macro cells is built into the part number. For example, the 9572XL has 72 macro cells. Each macro cell has a single flop and a single wide AND array. The AND array and flop can be used together or each separately. Ignore the data sheet stuff about gate count. It is always misleading.
The biggest limitation for Xilinx CPLD is the one flop per macro cell limit. 72 flops is not alot especially when you try to do things like FIFOs or memory. CPLDs are NOT miniature FPGAs. FPGAs have a large, large number of internal LUTs and flops. CPLD have their logic restricted to macro cells at the IOB.