How long does it take for a pulldown resiter to bring logic 1 to 0 ?

[lostinxlation]

How long does it take for a pulldown resistor to bring logic 1 to 0 ?

One of the designs I have has a bi-directional IO with a pulldown, and, at some occasion, the IO is configured as an output driven by 1, and then output enable to the IO gets deasserted, which leaves the IO high impedance. I'd expect the logic level to come down to 0 through a pulldown resistor, but I don't see that's happening and the IO net remains high. May not be a good design to use the pulldown resistor to discharge the IO net that is fully charged, but, besides that, how long does it usually take for a pull down resistor to bring the logic level 1 to 0 ?

The FPGA is Virtex4, using ISE13.1 for synthesis/P&R.

 

[enjunear]

It all depends on what is connected to the line. If the pin is truly an open-collector style logic, then just about any pull-down resistor (10k-100k) should be sufficient to discharge the minimal part capacitance and pull the line low. If the line is staying high, even with a moderate pull-down (10k), I'd check all of the circuits touching that net... something has to be keeping it high.

 

[IanP]

A weak pull-down will never bring the voltage down when something is still pulling it up, but if the circuit is purely capacitive have a look at the attached graph ..

:wink:
IanP

 

[yadog]

it's a issue about the specific RC circuit