How is timing closure performed.?

[limitless_21]

Hi All,

I am all new to this timing closure. Can anyone let me know what are the steps being followed for doing timing closure on a design. What are the factors we look for and what are the inputs and outputs for performing this.

Thanks
Limitless_21

 

[rahul.achates]

there should not be any setup/hold/recovery/removal/transition violations present in design , input will be constraint file and post layout netlist , output will be your generated reports.

 

[limitless_21]

there should not be any setup/hold/recovery/removal/transition violations present in design , input will be constraint file and post layout netlist , output will be your generated reports.

HI Rahul,

Thanks for your quick response. Can you give me the details of the inputs given to the tool. Like what all libraries are given, how is noise and crosstalk handled.
What are all the reports are generated at the end?

Thanks
Limitless_21

 

[sharath666]

Timing closure as the name indicates refers to closing the timing for the block under consideration. When I mean closing timing for the block, I mean that every timing path in that design should satisfy the timing set for that path(given under constraints).
For your 2nd question, the libraries are chosen very early in the design phase(taking power into consideration). If you are doing synthesis, the RTL will be the input. If you are doing pre layout STA, then your post synthesis netlist will be the input. For post layout STA, your post P&R netlist along with the SPEF will be used. You also have to provide the constraints in any of these runs.
You will get timing reports as output.

 

[limitless_21]

Hey Rahul,

Just wanted to know more details on timing closure - as to on which tool is it done, which level in the flow it is performed, what all files are needed for the tool to run , what all reports are being generated and what is the criteria we look for timing closure.
Thanks in advance.

Regards
Limitless