How is the read and write latency calculated in a syncronous sram

[dll_fpga]

Read latency is calculated from the point oe is asserted and data is outputted by the ram.
write latency is calculated from the point we is asserted and write data is sampled.
Is that true?
any documents or suggestions?

 

[rca]

if your memory is synchronous as mention in the header, the pin clk will involve in the timing.

 

[dll_fpga]

if your memory is synchronous as mention in the header, the pin clk will involve in the timing.

yes....syncronous.By oe and we asserted, i meant it is also sampled on the posedge of the clock.