Jasper Chow
Junior Member level 3
I'm learning cortex m3 based stm32f10xx mcus. I don't understand how the program counter value of Cortexm3 is caculated.
The definitive guide to cortex m3 states,
" when you read this register, you will find that the value is different than the
location of the executing instruction, normally by 4. For example:
0x1000: MOV R0, PC ; R0 = 0x1004
In other instructions like literal load (reading of a memory location related to current PC value), the
effective value of PC might not be instruction address plus 4 due to alignment in address calculation.
But the PC value is still at least 2 bytes ahead of the instruction address during execution."
Here is the pseudocode explanation of BL instruction specified by ARMv7-m architecture reference
"if ConditionPassed() then
EncodingSpecificOperations();
next_instr_addr = PC;
LR = next_instr_addr<31:1> : ’1’;
BranchWritePC(PC + imm32);"
My question is if PC is normally 4 ahead of current executed instruction, how can it be the address of the next instruction since cortexm3 only employ thumb instructions? Some information I googled says the PC is a pointer to the the instruction being fetched, and cortex m3 has three-stage pipeline, so PC's value is the address of the instruction after next instrution. If so, the instruction following BL will not be exexcuted after the subroutine returns.
I coundn't find any detailed machanism of the PC calculation and instruction execution process from any related documents issued by ARM. Someone help me
The definitive guide to cortex m3 states,
" when you read this register, you will find that the value is different than the
location of the executing instruction, normally by 4. For example:
0x1000: MOV R0, PC ; R0 = 0x1004
In other instructions like literal load (reading of a memory location related to current PC value), the
effective value of PC might not be instruction address plus 4 due to alignment in address calculation.
But the PC value is still at least 2 bytes ahead of the instruction address during execution."
Here is the pseudocode explanation of BL instruction specified by ARMv7-m architecture reference
"if ConditionPassed() then
EncodingSpecificOperations();
next_instr_addr = PC;
LR = next_instr_addr<31:1> : ’1’;
BranchWritePC(PC + imm32);"
My question is if PC is normally 4 ahead of current executed instruction, how can it be the address of the next instruction since cortexm3 only employ thumb instructions? Some information I googled says the PC is a pointer to the the instruction being fetched, and cortex m3 has three-stage pipeline, so PC's value is the address of the instruction after next instrution. If so, the instruction following BL will not be exexcuted after the subroutine returns.
I coundn't find any detailed machanism of the PC calculation and instruction execution process from any related documents issued by ARM. Someone help me
