How is an integrator + limiter circuit designed, and how does it work?

[tsmith35]

I'm trying to set up a circuit to limit the acceleration of a drive. The drive accepts 0-10V for speed control, which is accomplished by a standard rotary pot that the operator turns. To prevent the operator from going from 0 to full speed in the swipe of a hand, I'd like to limit the acceleration to (say) 1V/sec. The operator can turn the knob to 50%, and the drive will ramp up to half speed over 5 seconds and hold at that point.

I saw a post from FvM describing such a circuit, but I have no idea how to calculate the values required to provide a specific ramp rate. :-( Can anyone help or point me in the right direction?

 

[chuckey]

See here :- https://en.wikipedia.org/wiki/Op_amp_integrator
Frank

 

[crutschow]

Below is a circuit the uses slew limiting and feedback to do what you want. U1's output goes to either supply rail when the input is changed (U1's output polarity depends upon the direction of the input change). This voltage is integrated by the integrator (U2), giving a linear voltage ramp. When the ramp reaches a level equal to the input value then the feedback causes U1's output to go to 0V at which point the integration stops and the integrator stays at the same voltage as the input.

V1 simulates a 0 to 10V and 10V to 0V instantaneous change of the control pot. Replace V1 with the pot connected to 10V and ground with the wiper going to U3's plus input. The integrator time-constant is selected to give a 1V/s slew rate or 10s for a full-scale change of 10V.

Edit: I noticed some oscillations at U1's output so I modified the circuit to reduce the gain of U1, which eliminated the oscillations and, since that reduced the input impedance of U1, I added U3 to buffer the pot output.

 

[tsmith35]

Crutschow, that's awesome! Thank you for figuring that out and providing all the details.

I guess it's time for me to learn how to make these circuits myself. I have just about everything (except time, of course). I have tons of books and components for learning electronics, but I never worked my way through any of it... Guess I can set aside an hour a night for learning.

 

[crutschow]

Learning to use a Spice type analog simulator, such as LTspice which is a free download from Linear Technology and what I used for the posted simulation, is a good way to experiment with different circuits. Then when you get the circuit working on LTspice, you can build it and see if the theory actually works. :wink:

Spice has a somewhat steep learning curve but it's well worth the effort. There's a tutorial and many example circuits included with the download to get you started.

 

[FvM]

Edit: I noticed some oscillations at U1's output so I modified the circuit to reduce the gain of U1, which eliminated the oscillations and, since that reduced the input impedance of U1, I added U3 to buffer the pot output.

Yes, this should work. Alterantively a PI gain stage as shown in the original post can be used to adjust the feedback loop for stability.
https://www.edaboard.com/threads/237851/#post1016986

 

[tsmith35]

Thanks for the help, guys! I d/l'd LTspice, so I'll fire it up tonight and see what I can break.

 

[tsmith35]

Okay, so everything looks good while testing in LTspice, but I noticed something while messing around with RC values. It appears that extending the ramp time out causes the output to go negative when starting up. Am I doing something wrong?

 

[crutschow]

Okay, so everything looks good while testing in LTspice, but I noticed something while messing around with RC values. It appears that extending the ramp time out causes the output to go negative when starting up. Am I doing something wrong?

No, the simulation is just warning you about some real, non-ideal aspects of the circuit. Try using uic (Skip initial operating point solution) in the transient command as I did in my simulation. With that the program doesn't calculate the initial DC circuit voltages which includes the offset of the opamps. These voltages will be significant with the large resistor values for R2 and R3 and cause the initial negative voltage.

Note that it would be difficult to build your circuit as shown in real life because of the high resistor values in conjunction with the input current and voltage offset of the opamps being used, and the leakage current of a 100uF electrolytic capacitor. Look in the LM324 data sheet to see these input bias and offset values.

The moral is that if the simulation shows you something you don't expect then you should take a closer look to see what it's trying to tell you. Sometimes it can be a anomaly in the simulation but more often then not, it's an actual artifact or error in your circuit design that may show up in the real circuit.

 

[FvM]

A reasonable implementation would use a 5 or 10 µF film capacitor, high Mohm resistors and FET OPs.

 

[tsmith35]

Thanks again, guys. I'm learning a lot about this as I go along. For some reason, "book" knowledge doesn't stick unless I have something practical to apply it against. Having fun right now...