How is "10% reduction in drain current" criterion related to MOSFET failure rate?

[AeroHeX]

How is "10% reduction in drain current" criterion related to MOSFET failure rate?

Hi, all,

I am studying the MOSFET failure due to Hot-Carrier Injection, and saw this criterion mentioned in all kinds of papers, but none gives the reason.

Is the MOSFET just considered as "bad" or "not-working" once reached this 10% reduction in drain current? Or, is this 10% reduction in Id will cause a certain failure rate (like a three sigma point? or one sigma? or some other meaning?) Or, more specifically, if an NFET in a digital logic gate circuit reaches the 10% reduction in Id, the circuit should still work till real breakdown happens, right?

Thank you very much for your time and answer!

 

[erikl]

Re: How is "10% reduction in drain current" criterion related to MOSFET failure rate?

I guess this rather arbitrarily looking "10% reduction in Id" limit concerns devices working in analog circuits, where such a current decrease presumably would mean "loss of intended/guaranteed accuracy" or even "loss of functionality" -- no direct relation to drop-out sigma failure rates.

But: which analog designer would risk HCI current biasing?

 

[AeroHeX]

Re: How is "10% reduction in drain current" criterion related to MOSFET failure rate?

I guess this rather arbitrarily looking "10% reduction in Id" limit concerns devices working in analog circuits, where such a current decrease presumably would mean "loss of intended/guaranteed accuracy" or even "loss of functionality" -- no direct relation to drop-out sigma failure rates.

But: which analog designer would risk HCI current biasing?

Thank you for your reply. I asked in this "analog design" board because I thought analog designers would know this kind of issue better. The situation is indeed for digital logic gates, when the FETs could experience HCI during logic state transitions. Many papers derived the relationship between the "in-circuit AC lifetime" and "DC stress lifetime". I just couldn't find any evidence saying any failure rate analysis after it reaches the 10% degradation.

Thank you.

 

[dick_freebird]

Re: How is "10% reduction in drain current" criterion related to MOSFET failure rate?

It is arbitrary but seems fairly common. However that onion
wants peeling, particularly in SOI technologies where there
may be some time-zero built in charge that gets baked out
and never comes back; your 10% drift, if it flatlines, might
not be an issue in fact but 10% that does not saturate, is
a good enough place to call lifetime done.

You don't want to stop at that point, you want to record
time and keep on going if you're interested in understanding.

 

[shabazmondal]

Re: How is "10% reduction in drain current" criterion related to MOSFET failure rate?

10% reduction in drain current is an indication that your channel is not getting formed properly.
This might be due to the several reasons which like hot electron effect and many more..
But the main thing is that the channel isn't getting formed properly.Hence a malfunction.

 

[dick_freebird]

Re: How is "10% reduction in drain current" criterion related to MOSFET failure rate?

At only 10% drift the channel is definitely still there. It's not
a malfunction unless your circuit is designed sensitive to that
level of drift. Obviously even things like temperature cause
way more variation than that and the channel is still there.

But a device which drifts out of step with its siblings is not
very good for analog matching (you may see a 5% criterion
for a mixed signal process while digital is fine with 10%);
again, an arbitrary sort of limit because there simply needs
to be a limit in order to have a pass / fail result. As well
as having something to control the process against, for
reliability.

I have designed a great many circuits where drifts are
well greater than 10%, for other reasons. You take the
data, you model, you design against. But always there
are boundary conditions.