How I can read/write to the following blockram RAM model ?

[RRRED]

Hello,

Can someone point me out how I can read/write to the following blockram RAM model ?

I can read and write to external SRAM, but I am not able to make this work using blockram. Could someone help?

ENTITY vram8k IS
	PORT
	(
		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		rdaddress		: IN STD_LOGIC_VECTOR (12 DOWNTO 0);
		rdclock		: IN STD_LOGIC ;
		rden		: IN STD_LOGIC  := '1';
		wraddress		: IN STD_LOGIC_VECTOR (12 DOWNTO 0);
		wrclock		: IN STD_LOGIC ;
		wren		: IN STD_LOGIC  := '1';
		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
END vram8k;

Instantiation:

	vram8k_inst : work.vram8k PORT MAP (
		data	 	=> v_data_sig,
		rdaddress 	=> v_address_r_sig(12 downto 0),
		rdclock	 	=> Clk_Z80,
		wraddress	=> v_address_w_sig(12 downto 0),
		wrclock	 	=> Clk_Z80,
		wren	 	=> vram_we_sig,
		rden	 	=> vram_re_sig,
		q			=> vram_q_sig
	);

I have tried a lot, and at this time, I have the following assertions for read/writing to the memory:

	v_address_w_sig <= A - x"2000" when (A >= x"2000" and MReq_n = '0');
	v_address_r_sig <= A - x"2000" when (A >= x"2000" and MReq_n = '0');
	vram_we_sig <= Wr_n;
	vram_re_sig <= Rd_n;
	v_data_sig <= DO_CPU when (Wr_n = '0' and MReq_n = '0');
        DI_CPU <= vram_q_sig when (Rd_n = '0' and MReq_n = '0' and A >= x"2000");

What must be changed for this to work?

Thanks.

 

[saleheen]

Re: Block RAM

Can you use LPM to design this RAM?

Added after 4 minutes:

I have one example of a 8-Bit RAM using LPM to design.. Hope this helps you..

 

[RRRED]

Re: Block RAM

Can you use LPM to design this RAM?

Added after 4 minutes:

I have one example of a 8-Bit RAM using LPM to design.. Hope this helps you..

Thank you for the file.
But I need a RAM for video buffer. It must have different ports and control signals for read / write operations.

thanks.

 

[RRRED]

Re: Block RAM

Any ideias?

Little explanation:

It is a SoC based on Z80.

When Z80 writes to RAM, it must be above 0x2000h.
When it reads, it can be ROM (0x0000h to 0x1FFFh), or RAM (above 0x2000h).

In the simulation (only the RAM model, not the full SoC), the read operations returned the data only on the 3rd clock cycle.

But, starting over, this is the code I understand you guys suggested:

	-- Write into RAM
	vram_wraddress_sig <= A - x"2000";
	vram_wren_sig <= (not Wr_n) or (not MReq_n) when A >= x"2000";
	vram_data_sig <= DO_CPU when Wr_n = '0' and MReq_n = '0' and A >= x"2000";

	-- Read from RAM
	vram_rden_sig <= '1';
	vram_rdaddress_sig <= A - x"2000";
	DI_CPU <= vram_q_sig when (Rd_n = '0' and MReq_n = '0' and A >= x"2000") else
			D_ROM when (Rd_n = '0' and MReq_n = '0');



	vram8k_inst : work.vram8k PORT MAP (
		data	 	=> vram_data_sig,
		rdaddress	=> vram_rdaddress_sig(12 downto 0),
		rdclock	 	=> Clk_Z80,
		rden	 	=> vram_rden_sig,
		wraddress	=> vram_wraddress_sig(12 downto 0),
		wrclock		=> Clk_Z80,
		wren	 	=> vram_wren_sig,
		q	 	=> vram_q_sig
	);

The write operations are OK?

What may I change to read correctly from RAM? (above 0x2000h in Z80, which is 0x0000 in RAM) ?

Thanks again.