Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How Gray counter promote overpowering GLITCH???

Status
Not open for further replies.

khaila

Full Member level 2
Joined
Jan 13, 2007
Messages
121
Helped
5
Reputation
10
Reaction score
1
Trophy points
1,298
Activity points
2,105
I already read an article regards Aync FIFO:
http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_FIFO1.pdf

As I know in order to overpower GLITCH while COMPARING two binary counters outputs, we may sampling the output compare by a FF. Then we will not have any GLITCHs.

The article, claims that we should use GRAY counter instead binary one; because one bit is changed at its output.

why?
why we should use GRAY counter to overpower GLITCHs? While if we will sample the output COMPARATOR then we will clean the GLITCHs!!!

how?
How this GRAY counter will overpower GLITCHs. GRAY sequence is that when ONE bit is changed, which means that when the the GRAY counter outputs is compared, anyway ONE bit may cause GLITCHs.
 

My understanding:
when using Gray counter,there's only 1bit toggle at one time.Therefore,you only need to judge this 1bit.
When using binary counter,maybe there are 2 or more bits toggle at one time,you need to judge these 2 bits to make a correct decision. Usually these 2 bits do not arrive at the same time,thus would cause greater glitch power.
 

eexuke said:
My understanding:
when using Gray counter,there's only 1bit toggle at one time.Therefore,you only need to judge this 1bit.
When using binary counter,maybe there are 2 or more bits toggle at one time,you need to judge these 2 bits to make a correct decision. Usually these 2 bits do not arrive at the same time,thus would cause greater glitch power.

But anyway we are comparing two bits simultanly, and those bits are not arriving at the same time which mean that there is a possibility for producing GLITCHs.

Supposed we have two counters with 4-bit each one, A[3:0] and B[3:0].
Then, anyway we are using 4 XOR gates for each bit.
when comparing A[3:0] and B[3:0] then we may get GLITCHs. It is not matter if all the bits of A and B are changed simultanly or only ONE bit in A and B changed simultanly, we always have GLITCHs if the bits are not arivied at the same time.

I agree that the possibility of reducing the glitch is less when one bit is changed than 4-bits is changed, but anyway we may have GLITCHs!!!

So why any the article consider using GRAY counter is to overpowering GLITCHs???
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top