How exactly boundary scan works

[deepen talati]

I wanted to know that how exactly boundary scan works? And Boundary scan logic is made for what? What does it test and what is it's function in DFT?

 

[electroM]

read this book:
Digital Systems Testing and Testable Design by Miron Abramovici, Melvin A. Breuer, Arthur D. Friedman.

 

[Barry Pearson]

Boundary-scan was devised as a method for testing manufacturing faults on PCBAs (assembled boards). Using a shift register that is isolated from the core of the device you can control a device's pins (provided it is compliant to the boundary-scan standard IEEE 1149), with appropriate hardware e.g. USB => boundary-scan (aka JTAG) controller and software.

Free getting started utilities for boundary-scan can be found at https://www.jtaglive.com and other sites.

A more focused book might be 'Boundary-scan Test A Practical Approach' by Bleeker, van den Eijnden and De Jong.

A concise introduction is at **broken link removed**

 

[deepen talati]

Thank you very much Barry Pearson.

 

[ro9ty]

One small addition ... though BScan is explained brilliantly here. Sometimes simple XOR and NAND gate logics are used instead of Boundary scan when the number of IO is small. This makes the logic simpler and easy to test.

 

[rca]

One small addition ... though BScan is explained brilliantly here. Sometimes simple XOR and NAND gate logics are used instead of Boundary scan when the number of IO is small. This makes the logic simpler and easy to test.

only XOR/NAND gate could do the same boundary function? I means, how the value in the boundary flops is save in your case?

 

[ro9ty]

only XOR/NAND gate could do the same boundary function? I means, how the value in the boundary flops is save in your case?

No RCA.. there is an ambiguity in what i have written here. Yhanks for pointing out.
No, only NAND/XOR gate cannot do the test because it cannot retain and pass test vectors. We had an internal bunch of registers known as non-test registers. What i mean bu NAND/XOR is that suppose there are 5 ports A B C D E. Now, we assume E to be output port always. With the functions inside and control bits we make few combinations like A nand B -> C nand D -> E and check in E. This is because we have a jtag in our core processor and we do not apply any external jtag for boundary.

Thanks
ro9ty