How duty cycle affects the performance of ADCs?

[asic_ant]

According to many Data Sheets(say AD9245,ADS5413),many high speed,high resolution ADCs employ a clock duty cycle stabilizer.
I just wander how clock duty cycle affects the performance of ADCs.
I also find that most ADCs employ such module are Pipeline ADCs.
Then what about other Architectures?
Any comments?Or any papers on this subject?
Thanks in advance!

 

[ricklin]

I think it is decided by the 2-phase non-overlap clock used in pipeline ADC. Pipeline's pass the signal between stages phase by phase, balance the 2-phase will make all stage easy to have enough time to settle their signal (excpet sample-hold stage may be need extra care).

 

[jerryzhao]

If In Pipeline ADC the clock high volgate the odd stage sample, the clock low voltage the even stage sample.
So the all stage must hvae enough time to do their work.At full speed u duty cycle not well maybe some stage's setting time not enough.
In high speed ADC u also need care the jitter of clock, that will take the aperture error to ADC.