Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
the above is a bootstrapped switch. the capacitor acts as a battery during p2, which is the output phase. during p1 the switch is off and the C is charged to vdd. during p2 the source to gate of the main switch is connected by the capacitor which has a constant voltage in it. hence the switch is much more linear, due to constant Vgs.
could anyone else comment on the above? whether it is right or wrong.