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# How does this circuit work??

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#### qslazio

##### Full Member level 3
this is a opamp used in bandgap
I only know that M1 M2 M3 M4 M5 are used to minimize the input systematic offset voltage.

But I cannot figure out how it works properly to do it.
Can anyone help me to describe the detail?

Thanks a lot!!!!

#### Alles Gute

##### Full Member level 2
M3 can be deemed as a curent source.
Then M1-M2, M4-M7 form a negative feedback, stabilize the gate voltage of M1/M6
to be value which (ideally) ensure zero systematic offset.
But are you sure the mirror ratio for M2 and M4 is 1:2 not 1:1?

#### wing

##### Newbie level 4
I don't think this circuit will improve the system offset, it may be worse. The only advatage is to increase the gain 2-4 times.

#### qslazio

##### Full Member level 3
Alles Gute said:
M3 can be deemed as a curent source.
Then M1-M2, M4-M7 form a negative feedback, stabilize the gate voltage of M1/M6
to be value which (ideally) ensure zero systematic offset.
But are you sure the mirror ratio for M2 and M4 is 1:2 not 1:1?

Alles Gute said:
M3 can be deemed as a curent source.
Then M1-M2, M4-M7 form a negative feedback, stabilize the gate voltage of M1/M6
to be value which (ideally) ensure zero systematic offset.
But are you sure the mirror ratio for M2 and M4 is 1:2 not 1:1?

Dear Alles Gute:
Ratio should be ok.
But the original circuit I got is like below, the defference is that the gate of M3 and M5 is connected, so i cut it out.
I thought it maybe a mistake because the pin pbias is a input bias which is relative stable and it should not be connect to a low impedence node(drain of M5).
If they are connected, all currents through all legs are stable.

Am I right to disconnect these nodes?

BTW: I can not see any feedback in M6 and M7 because the amplitude of v(opout) will not affect either gate voltage of M7 or gate voltage of M6.

#### Btrend

in my opinion, there is no feedback in M1,M2,M4-M7.
the circuit u added (M1-M5) is probably only to increase the gain of OP.
in talking about systematic offset, it is usually inverse proportional to the gain.
so increasing gain, reducing systematic offset.

#### Alles Gute

##### Full Member level 2
you are right, increase the gain of first stage can decrease the systematic offset referred to input.
However, if the extra circuit is just used for increasing gain, why not just increase the bias current of the differential pair? Yes, it will increase power, but this topology also use extra bias current and also use eatra devices.

what I thought about the feedback is like this:
Vg1 increase -> ID6 increase -> ID7,ID5,ID2 increase -> ID1 decrease ->Vg1 decrease.

I am not really sure. Hope to see more discussion.

#### Btrend

Vg1 increase -> ID6 increase -> ID7,ID5,ID2 increase -> ID1 decrease ->Vg1 decrease
i don't think "ID6 increase -> ID7,ID5,ID2 increase -> ".
cause ID7 is controlled by M5, it will only increase if only ID5 increase. they are current mirror. and M6 can not affect vgs5, so id7=gm7*vgs5 is not affected by M6.

#### kamalakkannan

##### Newbie level 6
hi ..

i see one more problem in sizing of last stage nmosM8.
u see in normal open loop case..
I(M10)=I
I(M3)=I
I(M1)=I(M2)=I/2
I(M4)=I(M5)=I(becuase of 1:2 ratio b/w M2 & M4).
I(M7)=4.5I
but I(M8) nmos =2.25I.
I(M7) not equal to I(M8).
this is not balanced DC bias condition.this itself will give little extra offset in the openloop.
COMING BACT TO VG1 analysis.
when VG1 by V+Dv,then I(M1)=I/2+Di ,I(M2)=I/2-Di,so VGS(M2) reduce.
I(M4)=I(M5)=I/2-Di,I(M7)=4.5I-4.5Di,I(M8)=4.5I+4.5Di(assuming that M8 size is 9/2 to 19/2..From 2.25I to 4.5I).
so opout decreases when VG1 increases.
bacically this architecture is another way of getting extra gain and extra settling response too..(last satge can source as well sink small signal current in better way than ordinary opmap.)

if any thing wrong,plz let me know.

#### fantaci

##### Member level 3
I think maybe you are wrong. you should not disconneted those nods. because I think it is where the feedback happens. I guess the pbias is from some diode connected transisitor and this transistor is connected to some current source. So why not analize by including bias circuit. When you do so, you can deem pbias as a current source bias, not a voltage source bias.
just my guess

#### willyboy19

##### Full Member level 3
I don't think the purpose of M1~M5 has anything to do with systematic offset. This is a clever designed OPAMP with push-pull output stage. You should think of M1~M5 as level shifter block which provides another replica of amplified output voltage from the first stage to the PMOS driver M7. The operating principle is current-mode based and provides minimum phase shift, which of course, has little impact on the close loop stability of the overall Opamp.

Challenge me if you think it differently

#### marshel

##### Member level 2
So this amp does not need any cap for compensation?

#### yuanxiao

##### Newbie level 4
please refer " Marc G. Degrauwe et al. "Adaptive Biasing CMOS Amplifiers" IEEE JSSC, vol. 17, June 1982"

#### qslazio

##### Full Member level 3
marshel said:
So this amp does not need any cap for compensation?
yes, it need compensation.
But I got rid of it in the above figure for the sake of simple analysis. It's a simple miller compensate strategy using source follower to block feedthrough path.

willyboy19 said:
I don't think the purpose of M1~M5 has anything to do with systematic offset. This is a clever designed OPAMP with push-pull output stage. You should think of M1~M5 as level shifter block which provides another replica of amplified output voltage from the first stage to the PMOS driver M7. The operating principle is current-mode based and provides minimum phase shift, which of course, has little impact on the close loop stability of the overall Opamp.

Challenge me if you think it differently

Thank willyboy19!
what about the noise of current mode circuit? Is it larger or smaller than voltage mode circuit?

#### willyboy19

##### Full Member level 3
The noise performance of this circuit should be about the same as the traditional voltage mode counterpart: the low frequency noise performance should be dominated by the first stage, while the high frequency noise behavior needs more attention due to the existance of zero introduced by the compensation cap.

You can analyze or simulate the noise behavior with circuit simulator to dig out more detailed info. Have fun!

#### dreamteam

##### Newbie level 6
Hello everybody,

Transistors M1, M2, M3 are a current substractor circuit. with this kind of circuit you can drive your push pull output stage with the differential pair output and it's complementary signal genrated by the substractor.

The connection between M5 and M3 would probably makes and auto-bias circuit.

#### pillar_chen

##### Member level 3
it is an push-pull output OTA. As for compenstion, it denpends on the poles.

#### ipsc

##### Member level 4
fantaci said:
I think maybe you are wrong. you should not disconneted those nods. because I think it is where the feedback happens. I guess the pbias is from some diode connected transisitor and this transistor is connected to some current source. So why not analize by including bias circuit. When you do so, you can deem pbias as a current source bias, not a voltage source bias.
just my guess

As suggested by fantaci, for the time being let us consider that 'pbias' is a current source bias and assume that gates of m3 and m5 are connected.

Now M2-M4-M5 form a feedback. This feedback ensures that
I(m2)=½*I(m3)=I(m1); But I(m3)=I(m10) => I(m1)=½*I(m10);

For V-differential=0, I(m11)=½*I(m10) and since I(m1)=½*I(m10) => gate voltages of of m11 and m1, i.e. drain voltage of m11=m12 => zero systematic offset.

However it's not clear to me why m6 is not properly sized. Can somebody through some light on this?